1. Field of the Invention
The disclosed subject matter relates generally to the fabrication of semiconductor devices and, more particularly, to forming a pattern placement error compensation layer.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
One technique for patterning vias is extreme ultraviolet light lithography (EUVL). EUVL techniques employ an off-axis illumination angle (e.g., 6 degrees). The off-axis illumination requires the use of reflective masks. One consequence of the off-axis illumination angle is telecentricity and shadowing errors which manifest as a pattern shift relative to the mask. An absolute pattern shift can compromise process margins by misaligning connections. An example of such misalignment could occur between vias and underling features. Typical device layouts include an amount of overlap area between layers above and below a feature that should all connect to attempt to compensate for some degree of alignment error. However, the overlap area is compromised when pattern shift occurs, which may result in a degradation in device performance. The net shift will be different in magnitude and direction for various features printed with the same mask.
The present application is directed to various methods for forming a pattern placement error compensation layer so as to eliminate or reduce the effects of one or more of the problems identified above.